Slow EEPROM reduces maximum oscillator frequency

In my previous post, I had written about having difficulties with the AT89C52’s oscillator being unstable and how I cured that issue.

Once I had achieved a stable oscillator, I increased the clock to 20 MHz.  All seemed to work properly.  I was able to write a BASIC program and save it to EEPROM using the PROG command and then I was able to run that same program from EEPROM as expected.  However, on a few occasions, the saved program ended up with hard-errors in it.  Looking at the saved program, one could see that some characters had changed and that in fact, the program had been a little trashed.  Erasing the EEPROM and saving again seemed to cure the problem but coming back to the project overnight and similat errors occurred.  At first, I thought that it might be a bad EEPROM, so I used a different one but the same type of “trashed saved program” errors occurred.  I even pulled the EEPROM to read in my TL-866A and I could see that a byte had in fact, changed.

I figured that it HAD to be the access time of the EEPROM getting in the way but I had not actually calculated the required timings to verify this. Well, I finally set up a spreadsheet to do so.  I used the timing formulas from the AT89C52 datasheet since those are the only timing variables that will change depending on the clock speed.

From the AT28C64-150’s datasheet, it can be seen by the”CE to output delay” parameter, that the data will be available no more than 150 nS after the CE line goes low.  The “Address to output delay” parameter is the same as the “CE to output delay” parameter of 150 nS.  Since I am using a GAL22V10D-15 to decode chip-selects and output enables for the RAM and EEPROM, I must take into consideration the propagation delay for the “Input or I/O to Combinatorial Output” parameter, which is 15 nS maximum.  What I found was that the 150 nS EEPROM was exactly at the maximum access time of 150 nS required for proper operation with the AT90S52 at 20 MHz, which explains the funky intermittent failures.  At 16 MHz, the EEPROM access time is within the required minimum timing.

Now, one may be asking “What about the RAM?  Is it not affected as well?”  The answer is “no”, because the RAM I am using is static and has a 15 nS access time.

Below are screen prints of the spreadsheet I used for this timing calculation.  On the left is the 20 MHz timing and the right is the 16 MHz timing.

Here is the spreadsheet file in XLS format.

Unless I decide to purchase some 120 nS AT28C64’s, I’ll leave the AT89C52 running at 16 MHz.

Still awaiting the AT89S52’s to arrive…


One thought on “Slow EEPROM reduces maximum oscillator frequency

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